A "right remedy" for Ethernet Mac and Phy layer problems

In today's digitally connected world, Ethernet, as the cornerstone of network communications, supports our daily Internet life, enterprise data transmission, and industrial automation control. However, just like cracks in the foundation of a building, Ethernet's MAC (Media Access Control) layer and PHY (Physical Layer) layer often face various problems. These problems are like "reefs" hidden in the network, threatening the stability and smoothness of data transmission.

From packet loss and bit errors in data transmission to unstable connections and limited rates, these MAC and PHY layer problems may inadvertently cause many troubles in our work and life. But don't worry, just as sailors have methods and skills to deal with reefs, in the world of networks, we also have a series of effective solutions to resolve these MAC and PHY layer problems and restore the clarity and smoothness of Ethernet transmission. Next, let's explore the secrets of these solutions together.

1. Introduction

1.1 What is the MAC layer?

In Ethernet, the MAC (Media Access Control) layer is an important part of the data link layer and is responsible for many key functions. First of all, it is responsible for controlling the physical medium that connects to the physical layer. It is the key bridge for the interaction between the data link layer and the physical layer, and determines how the data flows to the physical layer for transmission. For example, when sending data, the MAC protocol will pre-judge whether the data can be sent at the moment. If conditions permit, it will add corresponding control information to the data, and then send the data to the physical layer in the prescribed format; when receiving data, the MAC protocol will first determine whether there is a transmission error in the input information. If there is no error, it will remove the control information and pass the data to the upper LLC (Logical Link Control) layer.

Secondly, the MAC layer is responsible for encapsulating data into frames. When data from the upper layer (such as the LLC layer or the network layer) arrives at the MAC layer, it will add a MAC header and possible trailer to the data to form a complete MAC frame. Correspondingly, after receiving the MAC frame, the MAC layer will also remove the header and trailer of the frame, extract the useful data and pass it to the upper layer to complete the decapsulation operation. Furthermore, processing the target and source MAC addresses is also an important responsibility of the MAC layer. As a globally unique hardware address, the MAC address is used by the MAC layer to identify each device on the network, so as to clarify which device the data is sent from and to which device it should be sent, so as to achieve accurate data transmission positioning.

Finally, the MAC layer also has the function of performing transmission error calibration. It can detect whether errors occur during data transmission through technologies such as cyclic redundancy check (CRC). Once an error is detected, the problematic frame will usually be discarded and may be required to be retransmitted to ensure the integrity and accuracy of data transmission and to ensure that data in the LAN can be transmitted correctly, efficiently and reliably.

1.2 What is the PHY layer

As a key part of realizing the physical layer function in the OSI model, the PHY layer plays an indispensable role in the Ethernet data transmission process.

On the one hand, the PHY layer will further encode the data sent by the MAC. For example, under different Ethernet standards, the encoding methods are different. Under the 100Base-TX standard, the data of the MAC layer must first be 4B/5B encoded, and then serial-to-parallel converted. The converted serial code stream will then go through a series of operations such as NRZI encoding, scrambling, and MLT-3 encoding before the subsequent transmission process; when receiving data, it will perform decoding and other operations in the opposite order to restore the received data to a form that the MAC layer can recognize and process.

On the other hand, the PHY layer is responsible for the conversion of digital signals and analog signals. When sending data, it converts the digital signal received from the MAC layer into an analog signal so that it can be transmitted on a physical medium (such as a network cable, etc.); when receiving data from the outside, it converts the analog signal back into a digital signal and then passes it to the MAC layer for subsequent processing.

At the same time, the PHY layer contains multiple sublayers, each with a clear division of labor. Among them, the PCS (physical coding sublayer) is mainly responsible for the encoding and decoding, transceiver processing, management and control of signals, following the ISO/IEC8802-3 and IEEE802.3 standards. For example, the corresponding encoding and decoding of signals at the 100Base-TX rate is the responsibility of the PCS sublayer; the PMA (physical medium connection sublayer) further transmits the PCS code to various media, completes the serial-to-parallel and parallel-to-serial conversion, so that the data can adapt to different physical media transmission requirements; the PMD (physical medium dependent sublayer) is responsible for completing the physical connection to ensure that the data can be stably transmitted on the corresponding physical medium. These sublayers work together to ensure the realization of the data transmission function of the physical layer.

1.3 Connection method between MAC and PHY layer

In Ethernet, the MAC and PHY layers are connected through specific interfaces, among which MII (Media Independent Interface) and its derivatives and SMI (Serial Management Interface) play a key role. The relationship between them is that the PCI bus connects to the MAC bus, the MAC connects to the PHY, and the PHY connects to the network cable (of course, they are not directly connected, there is also a voltage transformer).

As a standard interface for connecting MAC and PHY, MII interface plays an important role. It includes multiple derivative versions, such as GMII (Gigabit Media Independent Interface) and RMII (Reduced Media Independant Interface), to adapt to different data transmission rates and application scenario requirements. From a functional perspective, MII interface covers the transmit data interface from MAC layer to PHY layer and the receive data interface from PHY layer to MAC layer, enabling data to be transmitted bidirectionally between MAC and PHY layers. For example, at a rate of 100Mbps, the clock frequency of the MII interface is 25MHz, and the data interface requires a total of 16 signals, supporting data rates of 10Mb/s and 100Mb/s, as well as full-duplex and half-duplex working modes, using 4bit to send and receive data; RMII is a simplified MII interface, which has twice as many signal lines (2 data bits) as the MII interface in data transmission and reception, and generally requires a bus clock of 50MHz. It also supports bus interface speeds of 10Mbps and 100Mbps, and is suitable for some application scenarios that require the number of signal lines; GMII is an interface that appears to support Gigabit network ports. The more commonly used RGMII reduces the number of pins between MAC and PHY on this basis, adopts a method of mixing data signals and control signals, and samples at the rising and falling edges of the working clock at the same time, meeting the data transmission requirements of Gigabit Ethernet.

In addition, the SMI interface plays a key role in MAC's control over PHY. The SMI interface consists of two wires and runs in duplex mode, with MDC as the clock line and MDIO as the data line. It also supports access to multiple different PHY chips through the bus. Under this interface system, the MDIO bus only supports MAC as the master device and PHY as the slave device. Its basic characteristics include two-wire system , specific clock frequency (such as 2.5MHz) and bus communication mode, and the number of PHYs that can be connected at the same time is 32. Through the SMI interface, the MAC chip can actively poll the PHY layer chip to obtain its status information, such as the current connection speed of the PHY chip, the duplex capability, etc., and can issue corresponding command information, so as to determine and control the working status of the PHY and ensure the stable and orderly operation of the entire Ethernet communication system.

2. Common Problems Revealed

2.1 Hardware connection related issues

In the actual application of Ethernet MAC and PHY layers, problems in hardware connection often affect the normal communication between the two. Common situations include welding errors, line damage, and loose interfaces.

For example, welding errors may be caused by cold soldering or continuous soldering of pins when installing the PHY chip. Cold soldering will cause poor contact between the chip pins and the circuit board, and the signal transmission will be intermittent; continuous soldering may cause a short circuit between the pins, causing confusion in signal transmission, and thus affecting the data interaction between the MAC and PHY layers. For example, some engineers found that the device communication was abnormal during the debugging process. After careful investigation, they found that a key pin of the PHY chip had a cold soldering. After re-soldering, the problem was partially improved.

Line damage is also a problem that cannot be ignored. If the network cable is used for a long time or is pulled or bent by external forces, the internal wires may break, making it impossible for the analog signal converted from the PHY layer to be transmitted to the corresponding device through the network cable, or the digital signal from the MAC layer cannot smoothly reach the PHY layer for the next step of processing. In addition, if there is a short circuit or open circuit in the line connecting the MAC and PHY layers on the circuit board, it will also block the normal transmission of the signal.

Loose interfaces are also common. For example, if the RJ45 interface (common network port socket) is not plugged in tightly or becomes loose after long-term use, it will cause unstable physical connection, thus affecting data transmission and reception. Also, if the connection interface between MAC and PHY layer such as MII, RMII, GMII, etc. is loose, it will also cause data transmission errors or interruptions.

When you encounter MAC and PHY layer communication problems caused by hardware connections, the troubleshooting ideas are as follows:

First, visually check the hardware connection to see if there are obvious signs of line damage, loose interfaces, whether the chip is firmly welded, whether there are any abnormalities in the pins, etc. Secondly, use professional tools to detect, such as using a multimeter to measure the continuity of the line to determine whether there is a circuit break; for the power line, check whether the voltage is normally transmitted to the corresponding chip to ensure normal power supply; you can also use an oscilloscope to view the signal waveform on the signal line to determine whether the signal quality meets the requirements, etc. Through these basic troubleshooting directions, gradually locate and solve the problems in the hardware connection and restore normal communication between the MAC and PHY layers.

2.2 Power and reset issues

The status of the power supply and reset circuits has a critical impact on the operation of the MAC and PHY layers.

When the power supply is unstable, a variety of adverse situations may occur. For example, if the power supply voltage fluctuates, excessively high voltage may damage the electronic components inside the PHY chip, while too low voltage may cause the PHY chip to malfunction, such as not being able to be mounted normally in the system, making it impossible for the MAC layer to establish an effective communication connection with it. For example, if there is ripple interference in the power supply, it will affect the accuracy of the signal, causing errors in the PHY layer when performing tasks such as converting digital signals to analog signals, thereby affecting the entire data transmission process. Taking Ethernet devices in some industrial environments as an example, due to the presence of many large motors and other equipment on site, the power supply is easily disturbed, and the PHY chip often works abnormally due to unstable power supply, and cannot accurately convert the digital signals from the MAC layer into analog signals suitable for network cable transmission, resulting in data transmission failure.

Reset circuit abnormalities can also cause many problems. When the reset circuit does not work properly, such as the reset signal cannot be generated normally or the reset signal cannot be raised in time as required after reset, the PHY chip may not be able to complete initialization and cannot enter the normal working state. In some embedded devices, unreasonable reset circuit design or component failure will cause the PHY chip to be in an abnormal state after reset. Even if other conditions such as power supply are normal, it cannot work with the MAC layer, such as being unable to respond to control commands sent by the MAC layer through the SMI interface, and unable to complete operations such as automatic negotiation of speed and duplex mode.

For power and reset issues, you can adopt the following solutions:

For power supply problems, on the one hand, we need to ensure the stability of the power supply itself. We can use a voltage-stabilized power supply module to reduce the interference of external factors on the power supply voltage. On the other hand, during the circuit design stage, we should arrange filter capacitors and other components reasonably to filter the power supply, reduce the ripple factor, and ensure the purity of the power supply output. At the same time, we should strictly match the voltage, current and other parameters of the power supply according to the chip manual requirements to avoid abnormal chip operation due to parameter mismatch.

For reset circuit problems, first check whether the various components in the reset circuit, such as reset chip, resistors, capacitors, etc., are working properly, and whether there are any damage or poor welding. Then, use an oscilloscope or other tools to view the waveform of the reset signal to confirm whether the level maintenance time, rising edge and falling edge of the reset signal meet the requirements of the PHY chip. If not, adjust and repair the corresponding circuit to ensure that the reset circuit can complete the reset operation normally, so that the PHY chip and MAC layer can start working in the correct initial state.

2.3 Configuration and driver issues

In the application of MAC and PHY layers, problems in configuration and driver can also hinder the communication between the two.

If the driver does not set the control register bits correctly, the MAC and PHY will not be able to communicate normally. For example, when the corresponding bits are not set to let the MAC layer know that the link status of the PHY layer is ready, even if the physical link is normal, the MAC layer will not be able to exchange data with the PHY layer due to lack of accurate information, and ultimately will not receive any data. In addition, in the negotiation of speed and duplex mode, if the driver is not configured properly, the MAC and PHY layers cannot negotiate a consistent speed (such as 10Mbps, 100Mbps, 1000Mbps, etc.) and duplex mode (half-duplex or full-duplex), which will cause data transmission to be chaotic or even impossible. For example, after some network devices have replaced the new PHY chip, the driver has not been updated and adapted in time, and the registers have not been correctly configured to work with the new chip, resulting in the inability of devices to communicate normally.

To solve this type of configuration and driver problems, you can start from the following aspects:

The first step is to modify the driver. When using PHY chips from different manufacturers or different models, the relevant codes in the driver should be adjusted according to the characteristics of the chip and the requirements of the manual to ensure that the driver can accurately work with the PHY chip. For example, the definition and operation of the control registers of PHY chips from different manufacturers may be different. It is necessary to modify the code part of the driver for register reading and writing operations so that it can correctly configure the working mode, speed and other parameters of the PHY chip.

The second step is to correctly configure the registers. You need to have a deep understanding of the functions of various registers involved in the MAC and PHY layers, such as reading and writing the registers of the PHY chip through the SMI interface to set the working status of the PHY chip and obtain its status information. According to the standard IEEE specifications and the specific instructions of the chip manual, accurately write the corresponding values ​​to the registers to achieve the correct configuration of the MAC and PHY layers, ensure that they can communicate smoothly, negotiate the appropriate speed and duplex mode, and thus achieve stable and efficient transmission of Ethernet data.

If the operating system does not load the network card driver, although the network card is on the system device tree, the network card interface cannot be created. Can the network card actually receive data?

There are a lot of details here. I wrote a rough outline based on the Intel network card spec. I wanted to make it as popular as possible, so I didn’t deliberately use the terminology in the spec. In addition, although this article talks about MAC/PHY, the optical port card (SERDES) is similar.

1. After the PCI device is reset, it enters D0uninitialized (uninitialized D0 state, refer to the PCI power management specification). At this time, the MAC and DMA of the network card do not work, and the PHY works in a special low power state.

2. When the operating system creates the device tree, it initializes the device and the Memory Access Enable or the I/O Access Enable bit of the PCI command register is enabled, which is D0active. At this time, the PHY/MAC is ready.

3. If PHY is enabled, it should be able to receive data on the physical link. Otherwise, FLP/NLP cannot be received and PHY cannot establish a physical connection. However, such packets are usually sent intermittently.

4. The driver usually controls PHY through registers, such as automatically negotiating speed/duplex and querying the status of the physical link Link up/down.

5. After MAC is enabled, if the driver does not set a bit in the control register (CTRL.SLU), MAC and PHY cannot communicate, that is, MAC does not know that the PHY link is ready, so it cannot receive any data. After this bit is set, the PHY completes the auto-negotiation, and the network card will have a link change interrupt to know that the physical connection has been linked up.

6. Even if the link is up, MAC still needs to enable a bit of the receiver (RCTL.RXEN) so that packets can be received. If the network card is reset, this bit is 0, which means that all packets will be dropped directly and will not be stored in the network card's FIFO. Old network cards use this to turn off reception before the driver exits. The dynamic configuration of Intel's latest Gigabit network card's send and receive queues relies on this bit. The traffic must be turned off during the reconfiguration process.

7. Regardless of whether the driver is loaded or not, after a reset, the MAC address in the EEPROM of the network card will be written into the MAC address filter register of the network card. The driver can modify this register. Modern network cards usually support many MAC addresses, that is, MAC addresses can be set by software. For example, Intel's Gigabit network card supports 16 unicast MAC addresses, but only one is stored in the EEPROM, and the others are claimed and set by the software.

8. But if the driver is not loaded, the NIC is already in the device tree, and the operating system has completed the initialization of steps 1-2, the NIC's PHY should be working, but because no one sets the control bit (CTRL.SLU) to establish a connection between MAC and PHY, the MAC does not receive packets. This control bit will be set to 0 again during reset.

9. PHY can be powered on and off by software. In the power-off state, it will not receive data except for receiving management commands. In addition, PHY can also work in Smart Power Down mode, and enter power saving state when link down.

10. Some multi-port network cards have multiple network ports sharing one PHY. Therefore, disabling a certain network port in the BIOS does not necessarily turn off the power of the PHY. Conversely, you should also be careful to turn off the power of the PHY.

3. Communication method

MII (Media Independent Interface) is a standard interface for connecting MAC and PHY. It is an Ethernet industry standard defined by IEEE-802.3. MII interface provides interconnection technology between MAC and PHY, and between PHY and STA (Station Management). Media independence means that any type of PHY device can work normally without redesigning or replacing the MAC hardware. It includes a data interface and a management interface between MAC and PHY. MII interfaces include MII, RMII, SMII, SSMII, SSSMII, GMII, SGMII, RGMII, etc. Here is a brief introduction to MII and RGMII.

The MII interface mainly consists of the following three parts:

• Transmit data interface from MAC layer to PHY layer
• Receive data interface from PHY layer to MAC layer
• MDIO interface for register control and information acquisition between MAC layer and PHY layer

The MII data interface requires a total of 16 signals. The MII clock is 25MHz and the transmission rate is 10/100Mbps. So the characteristics of MII are as follows:

• Supports 10Mb/s and 100Mb/s data rates
• In 100M working mode, the reference clock is 25MHz; in 10M working mode, the signal reference clock is 2.5MHz
• Support full-duplex and half-duplex working modes
• When sending and receiving data, 4-bit mode is used

RMII is a simplified MII interface. It has twice as many signal lines (2 data bits) as the MII interface in data transmission and reception, so it generally requires a 50MHz bus clock. RMII is generally used in multi-port switches. All data ports share a common clock for all ports to transmit and receive, which saves a lot of ports. An RMII port requires 7 data lines, which is half as many as MII, so the switch can access twice as many data ports. Like MII, RMII supports 10Mbps and 100Mbps bus interface speeds.

Later, in order to support Gigabit Ethernet, the Gigabit MII interface, also known as the GMII interface, was introduced. RGMII is now more commonly used, which reduces the number of pins between MAC and PHY. The data signal and the control signal are mixed together and sampled at the rising and falling edges of the working clock. The corresponding relationship diagram is as follows:

• 10M bandwidth corresponds to 2.5MHz, because 4bit*2.5M=10Mbps
• 100M bandwidth corresponds to 25MHz, because 4bit*25M=100Mbps

1000M bandwidth corresponds to 125MHz. Because 250MHz frequency is too high, double-edge sampling technology is used (which will bring design complexity). 4bit125M2=1000Mbps

SMI is the MAC core access to the PHY register interface, which consists of two lines, duplex, MDC for the clock, MDIO for bidirectional data communication, in principle is very similar to the I2C bus, can also access multiple different phys through the bus.

MDC/MDIO basic features:

• Two-wire system: MDC (clock line) and MDIO (data line).
• Clock frequency: 2.5MHz
• Communication mode: bus system, the number of PHYs that can be connected simultaneously is 32
• Through the SMI interface, the MAC chip actively polls the PHY layer chip to obtain status information and issue command information.

When the PHY chip sends data, it receives the digital signal sent by the MAC layer, then converts it into an analog signal and transmits it through the MDI interface. However, the transmission distance of the network cable is very long, and sometimes it needs to be sent to an address 100 meters or even farther, which will cause signal loss. In addition, the external network cable is directly connected to the chip, and electromagnetic induction and static electricity can easily cause damage to the chip, so a network transformer must be used. Its main functions are:

To transmit data, it couples and filters the differential signal sent by PHY with a differential mode coupled coil to enhance the signal, and couples it to the other end of the connecting network cable of different levels through the conversion of electromagnetic fields;

Isolate the different electrical levels between different network devices connected by the network cable to prevent different voltages from damaging the equipment through the transmission of the network cable; it can also isolate the chip end from the outside, greatly enhance the anti-interference ability, and increase the protection of the chip to protect the PHY from damage caused by electrical errors (such as lightning strikes).

3.1MAC

MAC (Media Access Control), the media access control sublayer protocol, has two concepts: MAC can be a hardware controller and MAC communication protocol. This protocol is located in the lower half of the data link layer in the OSI seven-layer protocol, and is mainly responsible for controlling and connecting the physical medium of the physical layer.

MAC (Media Access Control), the media access control sublayer protocol, has two concepts: MAC can be a hardware controller and MAC communication protocol. This protocol is located in the lower half of the data link layer in the OSI seven-layer protocol, and is mainly responsible for controlling and connecting the physical medium of the physical layer.

Sending data: The MAC protocol can determine in advance whether data can be sent. If it can be sent, it will add some control information to the data and finally send the data and control information to the physical layer in a specified format.

Receiving data: The MAC protocol first determines the input information and whether a transmission error occurs. If there is no error, it removes the control information and sends it to the LLC (Logical Link Control) layer.

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The PHY physical layer is at the bottom of OSI. The physical layer protocol defines electrical signals, line status, clock requirements, data encoding, and connectors for data transmission.

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The MDI port is a media dependent interface defined by Fast Ethernet 100BASE-T. MDI refers to the 100BASE-T signal sent through the transceiver, that is, 100BASE-TX, FX, T4 or T2 signal. When connecting a hub to a network interface card, its transmit and receive pairs are usually connected to each other. When connecting hubs, a jumper cable is usually required, in which the transmit and receive pairs are reversed.

MDI is a normal UTP or STP connection, while the transmit and receive pairs of the MDI-X connector are reversed internally, which allows different devices (such as hub-hub or collector-switch) to be cascaded back-to-back using regular UTP or STP cables.

⑴MII interface

MII (Media Independent Interface) is a standard interface for connecting MAC and PHY. It is an Ethernet industry standard defined by IEEE-802.3. MII interface provides interconnection technology between MAC and PHY, and between PHY and STA (Station Management). Media independence means that any type of PHY device can work normally without redesigning or replacing the MAC hardware. It includes a data interface and a management interface between MAC and PHY. MII interfaces include MII, RMII, SMII, SSMII, SSSMII, GMII, SGMII, RGMII, etc. Here is a brief introduction to MII and RGMII.

The MII interface mainly consists of the following three parts:

• Transmit data interface from MAC layer to PHY layer
• Receive data interface from PHY layer to MAC layer
• MDIO interface for register control and information acquisition between MAC layer and PHY layer

First, let's look at the MII MAC layer definition interface: The MII data interface requires a total of 16 signals, including TX_ER, TXD[3:0], TX_EN, TX_CLK, COL, RXD[3:0], RX_ER, RX_CLK, CRS, RX_DV, etc. The MII clock is 25MHz and the transmission rate is 10/100Mbps. So the characteristics of MII are as follows:

• Supports 10Mb/s and 100Mb/s data rates
• In 100M working mode, the reference clock is 25MHz; in 10M working mode, the signal reference clock is 2.5MHz
• Support full-duplex and half-duplex working modes
• When sending and receiving data, 4-bit mode is used

Purpose of RMII:

RMII is a simplified MII interface. It has twice as many signal lines (2 data bits) as the MII interface in data transmission and reception, so it generally requires a 50MHz bus clock. RMII is generally used in multi-port switches. All data ports share a common clock for all ports to transmit and receive, which saves a lot of ports. An RMII port requires 7 data lines, which is half as many as MII, so the switch can access twice as many data ports. Like MII, RMII supports 10Mbps and 100Mbps bus interface speeds.

Later, in order to support Gigabit Ethernet, the Gigabit MII interface, also known as the GMII interface, was introduced. RGMII is now more commonly used, which reduces the number of pins between MAC and PHY. The data signal and the control signal are mixed together and sampled at the rising and falling edges of the working clock. The corresponding relationship diagram is as follows:

• 10M bandwidth corresponds to 2.5MHz, because 4bit*2.5M=10Mbps
• 100M bandwidth corresponds to 25MHz, because 4bit*25M=100Mbps
• 1000M bandwidth corresponds to 125MHz. Because 250MHz frequency is too high, double-edge sampling technology is used (which will bring design complexity). 4bit125M2=1000Mbps

⑵SMI interface

SMI is the MAC core access to the PHY register interface, which consists of two lines, duplex, MDC for the clock, MDIO for bidirectional data communication, in principle is very similar to the I2C bus, can also access multiple different phys through the bus.

MDC/MDIO basic features:

• Two-wire system: MDC (clock line) and MDIO (data line).
• Clock frequency: 2.5MHz
• Communication mode: bus system, the number of PHYs that can be connected simultaneously is 32
• Through the SMI interface, the MAC chip actively polls the PHY layer chip to obtain status information and issue command information.

3.2PHY

The physical layer is at the bottom of OSI. The physical layer protocol defines electrical signals, line states, clock requirements, data encoding, and connectors for data transmission. The device at the physical layer is called PHY.

PHY is a physical interface transceiver that implements the physical layer of the OSI model. The IEEE-802.3 standard defines Ethernet PHY including MII/GMII (Media Independent Interface) sublayer, PCS (Physical Coding Sublayer), PMA (Physical Medium Attachment) sublayer, PMD (Physical Medium Dependent) sublayer, and MDI sublayer.

⑴MDI

The MDI port is a media dependent interface defined by Fast Ethernet 100BASE-T. MDI refers to the 100BASE-T signal sent through the transceiver, that is, 100BASE-TX, FX, T4 or T2 signals. When connecting a hub to a network interface card, its transmit and receive pairs are usually connected to each other. When connecting hubs to each other, a jumper cable is usually required in which the transmit and receive pairs are reversed. MDI is a normal UTP or STP connection, while the transmit and receive pairs of the MDI-X connector are reversed internally, which allows different devices (such as hub-hub or hub-switch) to be cascaded back-to-back using regular UTP or STP cables. "

⑵ Basic knowledge of PHY

PHY is a standard module specified by IEEE 802.3. SOC can configure PHY or read PHY related status through MDIO. The internal registers of PHY must meet

The register address space of the PHY chip is 5 bits, which is generally determined by the external hardware connection.

There are 32 registers in address space 031. IEEE defines the functions of 16 registers 015, and the 16 registers 16-31 are implemented by the manufacturer. In other words, no matter which manufacturer's PHY chip, the 16 registers 0 to 15 are exactly the same.

These 16 registers alone can fully drive the PHY chip, at least to ensure basic network data communication. Therefore, the Linux kernel has a universal PHY driver. In theory, no matter which manufacturer's PHY chip you use, you can use this universal PHY driver of Linux to verify whether the network is working properly. In fact, in actual development, some other problems may occur that cause the Linux kernel's universal PHY driver to work abnormally, and at this time, the driver developer needs to debug it.

As the performance of PHY chips is getting stronger and stronger, 32 registers can no longer meet the needs of manufacturers, so many manufacturers have adopted a paging mechanism to expand the register address space in order to define more registers. These extra registers can implement some unique technologies of the manufacturer, so you can see a lot of specific PHY chip driver source code in the Linux kernel.

4. There are some tricks to treat the symptoms

4.1 Hardware Level Solution

When you encounter hardware-related problems, the following methods may help you restore the hardware to normal operation:

Re-soldering : For MAC and PHY layer communication failures caused by welding errors, such as pin cold soldering or continuous soldering, re-soldering is required. For example, if a PHY chip pin is found to have a cold soldering, use professional welding tools to re-solder the cold soldered pin firmly to ensure good contact between the chip pin and the circuit board so that the signal can be transmitted stably; for continuous soldering problems, carefully separate the short-circuited pins and clean up the excess solder to ensure normal electrical connection between the pins.

Check the integrity of the line : In terms of the line, whether it is the network cable or the line connecting the MAC and PHY layers on the circuit board, it must be carefully checked. For the network cable, you can follow the direction of the network cable to check whether its outer skin is damaged or bent excessively. If you suspect that the internal wire is broken, you can use the resistance range of the multimeter to measure the resistance value of different cores of the network cable. Under normal circumstances, it should be a small resistance value. If the resistance value is infinite, it means that the core may be broken. At this time, you need to replace a new network cable. For the lines on the circuit board, also use the continuity test function of the multimeter to check whether there is a circuit break or short circuit fault. If the line is found to be damaged, it must be repaired or rewired in time to ensure that the signal can be transmitted normally through the line.

Replace the power module : When the unstable power supply affects the operation of the MAC and PHY layers, consider replacing the power module. For example, in some industrial environments, since the power supply is easily interfered with, if the original power module cannot provide a stable voltage output, you can choose a power module with better anti-interference ability and stronger voltage stabilization performance to replace it, to ensure that the output voltage meets the range required for the normal operation of the PHY chip and the MAC chip, to avoid abnormal chip operation due to voltage fluctuations, ripple interference and other problems, and affect data transmission.

Repair the reset circuit : When the reset circuit is abnormal and the PHY chip cannot be initialized normally to enter the working state, the reset circuit must be repaired. First, comprehensively check the various components in the reset circuit, such as the reset chip, resistors, capacitors, etc., to see if there is any damage or poor welding. If there are damaged components, replace them according to the original specifications; then, use an oscilloscope to view the waveform of the reset signal to confirm whether the level maintenance time, rising edge and falling edge of the reset signal meet the requirements of the PHY chip. If not, make corrections by adjusting the parameters of related components or repairing the circuit connection to ensure that the reset circuit can complete the reset operation normally, so that the PHY chip and the MAC layer can start working in the correct initial state.

4.2 Software Level Solutions

When dealing with configuration and driver-related issues, the following software operations can help the MAC and PHY layers coordinate and achieve normal data transmission:

Read and write registers : Reading and writing the registers of the PHY chip through the SMI interface is a critical operation. The register definitions and operation methods of PHY chips from different manufacturers and models will vary, and reading and writing should be performed according to the specific instructions in the chip manual. For example, in order to obtain the current connection speed, duplex capability and other status information of the PHY chip, data can be read from the corresponding register through the SMI interface according to the corresponding register address and reading rules; and to set the working status of the PHY chip, such as configuring its working mode, speed and other parameters, write values ​​that comply with IEEE specifications and chip requirements to the corresponding registers to ensure that the MAC and PHY layers can work according to the set status and ensure the normal development of data transmission.

Update driver version : When the PHY chip of different manufacturers or different models is replaced, the original driver may not be able to adapt to the new chip, so the driver version needs to be updated. According to the characteristics of the new chip and the manual requirements, the relevant code in the driver is adjusted and modified, especially the code part for the control register reading and writing operations, so that it can accurately work with the new PHY chip, and realize functions such as automatic negotiation speed, duplex mode, etc., to avoid the MAC and PHY cannot communicate normally due to driver mismatch, and the data transmission is disordered or interrupted.

Re-negotiation according to the specification : Normally, the automatic negotiation function is enabled by default, but sometimes the function cannot be used. At this time, it is necessary to confirm whether the MAC and PHY chips support the use of the automatic negotiation function. If it supports but does not negotiate normally, the automatic negotiation operation must be carried out in accordance with the IEEE specification. For example, in some specific network equipment combinations, if the automatic negotiation fails, the problem of not being able to determine the appropriate data transmission speed and duplex mode, you can manually configure the relevant parameters and guide the MAC and PHY layers to re-negotiate, so that they can reach a consensus working mode that can ensure stable data transmission, such as negotiating a speed of 100Mbps and full duplex mode.

4.3 Comprehensive inspection and maintenance suggestions

When encountering MAC and PHY layer problems, it is crucial to conduct a systematic troubleshooting. Here are some suggestions:

⑴ Systematic investigation steps

First check the hardware appearance and connection situation: intuitively check the hardware connection status, check whether there are obvious signs of line damage, interface looseness, whether the chip soldering is firm, whether there are any pin abnormalities, etc. For example, check whether the RJ45 interface is tight, whether the connection interface between MAC and PHY layers such as MII, RMII, GMII and GMII is loose; then check the PHY chip's soldering status, whether there are any false soldering, continuous soldering or pin damage. At the same time, observe whether there are short circuits, circuit breakers and other problems on the circuit board. For network cables, you should also pay attention to the integrity of the outer skin and whether there is a risk of breaking the wire.

Then check the software configuration, driver status, etc. in sequence: In terms of software, first check whether the driver is installed correctly and whether it is adapted to the current MAC and PHY chips, check whether the configuration of the registers in the driver meets the chip requirements, such as whether the control register bits are correctly set to make the MAC layer know the link status of the PHY layer and other key information. Then check the status of the software level through relevant tools, such as using the network management tools provided by the operating system or professional network detection software, check the working status parameters of the MAC and PHY layer, confirm whether the speed, duplex mode, etc. are negotiated successfully, and whether the data transmission is normal.

⑵ Daily maintenance suggestions

Regularly check hardware connections: Check the hardware connection parts such as network cables, interfaces, and chip pins at intervals, and promptly discover and deal with potential problems such as looseness and damage, so as to avoid serious communication failures caused by long-term accumulation.

Do a good job in power management and monitoring: Ensure the stability of power supply. For use environments that are prone to interference, power filtering and voltage stabilization equipment can be added; at the same time, regularly detect power supply voltage, ripple and other parameters, promptly detect power abnormalities and deal with it, to prevent the operation of the MAC and PHY layer chips from affecting the operation of power supply problems.

Update drivers and firmware in a timely manner: Pay attention to driver updates and firmware upgrade information released by MAC and PHY chip manufacturers, and perform update operations in a timely manner to ensure that the device can adapt to the latest functional optimizations and compatibility improvements, and reduce problems caused by excessive software versions.

Backup important configuration information: Back up important information such as correct configuration parameters, register setting values, etc. related to the MAC and PHY layer. When there is a failure, it can be restored to normal work quickly and accurately.