SPI subsystem SPI spec

1.SPI hardware

SPI: Serial Peripheral Interface, proposed by Motorola, is a high-speed, full-duplex, synchronous communication bus. SPI works in master-slave mode, usually with one master device and one or more slave devices, without a response mechanism.

In this article, we explain the standard 4-wire SPI. The four wires are as follows:

①CS/SS, Slave Select/Chip Select, chip select signal line, used to select the slave device that needs to communicate.

②SCK, Serial Clock, serial clock, like SCL of I2C, provides clock for SPI communication.

③MOSI/SDO, Master Out Slave In/Serial Data Output, master output slave input.

④MISO/SDI, Master In Slave Out/Serial Data Input, master input slave output.

2. Four working modes of SPI

SPI has four working modes, which are obtained by matching the clock polarity (CPOL) and the clock phase (CPHA):

 ①. CPOL = 0 , the serial clock idle state is low level.
 ②、CPOL = 1 , the serial clock idle state is high level.
 ③. CPHA = 0 , data is collected on the first transition edge ( rising or falling edge ) of the serial clock.
 ④. CPHA = 1 , data is collected on the second transition edge ( rising edge or falling edge ) of the serial clock.

The sample waveform is as follows:

SPI is full-duplex, so the read and write timings can be completed together.

3.SPI transmission mechanism

As can be seen from the figure, both the host and the slave have a serial shift register. The host initiates a transmission by writing a byte to its SPI serial register. The register transmits the byte to the slave through the MOSI signal line, and the slave also returns the contents of its shift register to the host through the MISO signal line. In this way, the contents of the two shift registers are exchanged.

The write and read operations of the peripheral are completed synchronously. If only a write operation is performed, the host only needs to ignore the received byte; conversely, if the host wants to read a byte from the slave, it must send a null byte to trigger the slave's transmission.

Although the SPI four-wire system supports simultaneous reading and writing, in fact, we often do not need to read and write at the same time, see the following two situations (refer to the BMA223 data sheet):

Note: The following three diagrams all have CPOL=1, CPHA=1

(1) The host writes data to the slave

The host sends 8 bits first. The first bit is 0, which means the host wants to write data to the slave. AD6~AD0 indicates the register address to be written. Then, the host will keep writing. During this period, SDO is always in high impedance state, which means it has been reading 1.

(2) The host reads data from the slave

In this case, the host first sends 8 bits, the first bit is 1, which means it is a read operation, then AD6 ~ AD0 are the register addresses to be read, and then SDO starts to return data.

4.SPI timing diagram

 Tcsb_setup: setup time
 Tcsb_hold: hold time
 tsckl: low level time
 tsckh: high level time
 SCK period: Tsckl + tsckh
 In general, Tsckl = tsckh

Note: The real waveform is as shown above. The high and low levels are not counted only when they reach the highest point. Below 0.3Vdd is a low level, and above 0.7Vdd is a high level. When calculating the signal time length, you need to pay attention to this tiny time. Hardware design must pay attention to signal quality risks, and software developers must also be able to read waveforms.

The parameters here do not need to be set in general SPI drivers, but these parameters can be modified in the SPI controller drivers provided by semiconductor manufacturers. When we write SPI drivers, we can modify these parameters according to the requirements of the slave device.

5.DMA and FIFO

Different platforms have different buffer size settings for SPI FIFO and DMA:

FIFO is used for transfers below 32 bytes, and DMA is used for transfers above 32 bytes.

DMA can automatically initiate multiple transfers, with a maximum of 256K at a time.

6. Comparison between I2C and SPI

The speeds of I2C and SPI are as follows:

SPI rate: tens of MHz or even hundreds of MHz, the speed depends on the CPU's SPI controller and clock

The SPI of STM32F103 supports up to 18MHz, and that of imx6ull supports up to 52MHz. Other chips generally do not use higher speeds because the faster the speed, the worse the waveform quality and the more likely it is to have problems.

The specific speed depends on the peripherals, for example, the SPI of W25Q128 EEPROM supports up to 80MHz, and the SPI of ICM20608 sensor supports up to 8MHz. Generally, the speed used on flash is faster.

7. Extensions

The SPI protocol actually includes three protocol interfaces: Standard SPI, Dual SPI and Queued SPI.

Dual SPI is still a four-wire system, but the transmission lines can be changed to the same direction, and the speed is twice that of Standard SPI.

Queued SPI is a six-wire system with two more data lines, and its transmission speed is four times that of Standard SPI.