Innovatively implement ultra-high bandwidth logic interconnection within FPGA using on-chip high-speed network (2D NoC)

An example of using NoC to optimize encryption and decryption design

Achronix's latest Speedster7t FPGA device based on TSMC's 7nm FinFET process includes a revolutionary new two-dimensional on-chip network (2D NoC). 2D NoC is like a highway network running on the FPGA programmable logic structure, providing ultra-high bandwidth (~27Tbps) for data transmission between FPGA external high-speed interfaces and internal programmable logic.

Figure 1 Speedster 7t FPGA structure diagram

The NoC distributes data across the FPGA using a series of high-speed row and column network paths, distributing data traffic horizontally and vertically across the FPGA fabric. Each row or column in the NoC has two 256-bit, unidirectional, industry-standard AXI channels that can run at a transfer rate of 512Gbps (256bit x 2GHz) in each direction.

NoCs offer several important advantages for FPGA design, including:

• Improve the performance of your design.
• Reduce idle logic resources and reduce the risk of placement and routing congestion in high-resource designs.
• Reduce power consumption.
• Simplify logic design and use NoC to replace traditional logic to perform high-speed interface and bus management.
• Achieve true modular design.

This article uses a specific FPGA design example to show the important role that NoC plays in the internal logic interconnection of FPGA. This design mainly implements the triple data encryption and decryption algorithm (3DES). This algorithm is a mode of the DES encryption algorithm. It applies the DES encryption algorithm three times to each data block and increases security by increasing the key length of DES.

In this FPGA design, we place the input and output pins in the four directions of the FPGA, top, bottom, left, and right. The data coming in from the top pin is decrypted by logic 1 and then sent to logic 2 through the blue trace for encryption before being sent out from the bottom pin. The data coming in from the left pin is decrypted by logic 3 and then sent to logic 4 through the red trace for encryption before being sent out from the right pin. As shown in Figure 2.

Figure 2 Backend layout and routing diagram of 3DES design (without NoC)

The problems encountered in this design are as follows:

• The connection delay between the encryption and decryption modules is too long. If pipeline registers are not added, the design performance will be greatly limited. However, since the connection bus width is 256 bits, adding several pipeline registers will occupy a lot of additional register resources.
• The connection buses between the upper and lower modules and the connection buses between the left and right modules cross each other. If the design is more complicated, local congestion in layout and routing may occur, which will greatly increase the layout and routing time of the tool.

The above two problems are also problems that most FPGA designers will encounter more or less in complex FPGA designs. The reasons may be that the design is more complicated, or it may be the limitation of the hardware platform, or the design must connect to peripheral Hard IP in different locations.

The emergence of NoC solves the above problems. NoC provides a bidirectional 288-bit raw data mode for the internal interconnection of FPGA logic. Users can use this 288-bit signal to directly connect logic or use custom protocol interconnection.

Figure 3 Using 2D NoC for internal logic interconnection

There are two network access points (NAPs) at each intersection of the NoC. Users can connect their own logic to the NoC and interconnect them simply by instantiating the primitives or macro definitions of the NAPs.

Figure 4 Network Access Point (NAP)

Figure 5 Example of instantiating NAP macro definition

In this way, by instantiating NAP on the 3DES encryption and decryption modules respectively, the NoC interconnection between the 3DES encryption and decryption modules can be realized.

Figure 6 3DES design (using NoC) back-end layout and routing diagram

This simplifies the user design while greatly improving the design performance from 260MHz to 750MHz. As shown in Figure 6, the large number of connection buses between logics are no longer visible. The bus connections are taken over by the NoC. Only the green clock routing and the white logic routing inside the module can be seen in the back-end layout and routing diagram.

This article mainly wants to show FPGA designers how to use NoC to interconnect the internal logic of FPGA through such an example, so as to provide FPGA designers with another way of thinking. When the performance cannot be improved and the layout and routing are congested in traditional FPGA design, can we consider using Achronix's new generation Speedster7t FPGA to simplify and accelerate the user's design?