Talk about the communication protocol I2C subsystem Hs Mode

1. I2C Hs-mode

Why is HS mode explained separately? Because high speed mode is very different from other modes.

0. Speed ​​up to 3.4MHz .
1. In Hs mode, the host SDAH has an open-drain output buffer, and SCLH has an output open-drain pull-down and current source pull-up circuit. This current source circuit shortens the rise time of the SCLH signal . At any time, only one host current source is valid in Hs mode.
2. In the Hs mode of a multi-master system, arbitration and clock synchronization are not performed to speed up bit processing. The arbitration process is usually completed after the master code is transmitted in the F/S mode.
3. The Hs-mode master device generates a serial clock signal with a 1:2 ratio of high and low levels, relaxing the timing requirements of setup and hold times.
4. You can also choose Hs-mode devices with a built-in bridge . In Hs-mode transmission, the high-speed data SDAH and high-speed serial clock SCLH lines of the Hs-mode device are separated from the SDA and SCL lines of the F/S-mode device through this bridge. The capacitive load of the SDAH and SCLH lines is reduced, making the rise and fall times faster.
5. The only difference between Hs-mode slave devices and F/S slave devices is the speed at which they operate. Hs-mode slaves have open-drain output buffers on the SCLH and SDAH outputs. An optional pull-down transistor on the SCLH pin can be used to stretch the SCLH signal low, but only after the acknowledge bit of an Hs-mode transmission.
6. The outputs of Hs-mode devices are glitch-free and the SDAH and SCLH outputs have a Schmitt trigger.
7. The output buffers of Hs-mode devices have slope control on the falling edges of the SDAH and SCLH signals.
8. The timing of the serial data SDA and serial clock SCL signals has been adjusted. Compatibility with other bus systems such as CBUS is not necessary, as they cannot operate at the increased bit rates.
9. If the power supply voltage of the fast-mode device is shut down, the SDA and SCL I/O pins must be left floating and the bus cannot be blocked.
10. The external pull-up device connected to the bus must be adjusted to accommodate the shorter maximum allowed rise time of the fast mode I2C bus. For a bus with a maximum load of 200pF, the pull-up device for each bus can be a resistor ; for a bus with a load between 200pF and 400pF, the pull-up device can be a current source (maximum 3mA) or a switch resistor circuit , as shown below:

Physical I2C bus configuration for systems with only Hs-mode devices.

The (optional) series resistor Rs protects the I/O of the I2C bus device from high voltage spikes on the bus and minimizes ringing and interference.

The two devices in the lower right corner are not only slave devices, but also master devices. There is an MCS current source during this period. If there are many devices on the bus, the bus capacitance will be large. Pulling up the bus voltage is equivalent to charging the capacitor, which takes time, which will cause the waveform to rise too slowly, so adding a current source can make the rising edge very fast.

1.data transfer format in Hs-mode

(1) START condition (S)

(2) 8-bit master code (0000 1XXX)

(3)Not-acknowledge bit (A)

2. Enable current source pull-up circuit in Hs mode

3. After the next repeated start condition, it is still in Hs-mode

As can be seen from the figure above, a Master code is sent in fast mode (FS mode), and then it switches to high-speed mode (HS mode) and sends the slave device address.

In the first stage, FS mode, the master device's code is sent and arbitration is performed. Therefore, there is no clock synchronization and arbitration in the high-speed mode stage.

The figure above is a schematic diagram of the complete communication waveform. First, send the host address in fast mode, and no slave response is required. Then switch to high-speed mode, send a reSTART, and then send the operation you want, read or write.