Talk about STM32 network interruption

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01 Introduction

Network interrupt vectors: one for normal network operation and another for Ethernet wakeup events (with wakeup frame or magic packet detection) when it is mapped to EXIT line 19

The first network interrupt is reserved for interrupts generated by the MAC and DMA, as described in the MAC Interrupt and DMA Interrupt sections.

The second interrupt is reserved for the interrupt generated by the PMT on a wake-up event. The mapping of the wake-up event to the EXIT line 19 causes the STM32F20X and STM32F21X to exit low-power mode and generate an interrupt.

When an Ethernet wakeup event mapped to EXIT line 19 occurs and the MACPMT interrupt is enabled and there is a rising edge on the EXIT line 19 interrupt is also enabled, they can both wake up the interrupt.

The RS bit (ETH_DMASR register) can be flexibly controlled using the watchdog timer (see ETH_DMARSWTR register). When this watchdog timer is programmed with a non-zero value, the watchdog timer is activated as soon as the RXDMA completes sending a received data frame to the system memory without triggering the receive state because it is not enabled in the corresponding receive descriptor (RDES1[31]). When the timer runs according to the programmed value, the RS bit is set to 1 and an interrupt occurs if the corresponding bit in the ETH_DMAIER register is enabled. The watchdog timer fails before running when a data frame is sent to the memory and RS is set to 1 because the timer is enabled for the descriptor.

Notice:

Reading the PMT control and status register automatically clears the received wakeup frame and received magic packet PMT interrupt flags. However, since the registers for these flags are located in the CLK_RX domain, there may be a significant delay before the firmware can see this update. This delay is particularly long when the RX clock is slow (in 10 Mbit mode) and when the AHB bus is high frequency.

Since the interrupt request from PMT to CPU is based on the same register in CLK_RX domain, the CPU may mistakenly call the interrupt routine a second time even after reading PMT_CSR. Therefore, the firmware may need to poll the received wakeup frame and received magic packet bits and exit the interrupt service routine only if they are both found to be '0'.

02Code

The network interrupt of STM32 should actually be the interrupt of the network-specific DMA. The data packets in the network conform to the 1518 rule, that is, they are 1460 bytes. The data packets received by MAC are 2K bytes. After each data packet on the network is received by MAC, an interrupt will be generated.

The official code is this

Obviously, the query method is used, and no interruption is used.

The interrupts are used as follows:

Configuring Network Interrupts

Comment out the query code provided by the official website.

After we use the interrupt form, the code is

With this code, we have no problem receiving data smaller than the data size of a DMA descriptor, and it is very smooth.

For more information about DMA descriptors, please refer to "DMA Controller for STM32 Network".

When receiving a large amount of data, errors will occur, the reception will be slow, and receiving too much will cause a crash.

The solution is:

Change if to while

In this way, the interrupt will be triggered after the entire data packet is received, thus solving this problem.

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