Detailed explanation of STM32 network DMA controller

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The block diagram of the STM32 network controller is as follows:

In the previous article we have explained:

①External PHY Interface: "STM32 Network Circuit Design"

②MAC controller: "STM32MAC controller"

Next we explain Part ③, the DMA controller of the STM32 network.

01DMA controller operation

The DMA has autonomous transmit and receive engines and a CSR (Control and Status Register) space. The transmit engine transfers data from the system memory to the TxFIFO, while the receive engine transfers data from the Rx FIFO to the system memory.

The controller (that is, DMA) uses descriptors to efficiently move data from a source address to a destination with minimal CPU intervention. DMA is designed for packet-oriented data transfers (such as frames in Ethernet).

The controller can be programmed to interrupt the CPU, for example upon completion of transmit and receive frame transfer operations and other normal/error conditions.

DMA communicates with STM32F20x and STM32F21x through the following two data structures:

1. Control and Status Register (CSR)
2. Descriptor list and data buffer.

The DMA controller sends the received data frames to the receive buffer of the STM32F20x and the memory of the STM32F21x. It can also send data frames from the transmit buffer of the memory of the STM32F20x. The descriptors located in the memory of the STM32F20x point to these buffers.

There are two descriptor lists: one for receiving and one for sending.

The DMA descriptor is shown in the figure below. The left side is a ring structure and the right side is a chain structure.

02DMA Descriptor

The Ethernet driver library stm32f2x7_eth.c provided by ST uses a link structure, which is as follows:

Descriptor Notes:

1. An Ethernet packet can span one or more DMA descriptors

2. One DMA descriptor can only be used for one Ethernet packet

3. The last descriptor in the DMA descriptor list points to the first one, forming a chain structure!

Descriptors are divided into enhanced descriptors and regular descriptors. We will only talk about regular descriptors! Because our network routines only use regular descriptors. Regular descriptors and enhanced descriptors have different structure member variables. Regular descriptors only use the first 4 member variables of the descriptor.

Note: The descriptor mentioned here has no hardware structure and is not a register. It is a purely software concept.

So how do descriptors relate to hardware?

The essence of the descriptor is that we use the structure to implement the descriptor ourselves, and then write the first address of the descriptor into the [ETH_DMATDLAR] register. The STM32 knows that this piece of memory is used as a send descriptor.

Conventional descriptors and enhanced descriptors are divided into two types: sending descriptors and receiving descriptors.

The following figure is a conventional TxDMA descriptor:

TDES0 is mainly used to indicate the status and control information of the descriptor.

TDES1 indicates the effective length of the descriptor buffer data.

TDES2 represents the address of the descriptor buffer. The data we want to send is placed in the memory pointed to by this address.

TDES3 indicates the address of the next descriptor.

Sending process:

1. When the OWN bit is 0, it means that the CPU can copy the data to be sent to the descriptor. After the copy is completed, we manually set the OWN bit of the descriptor to 1 to tell the DMA controller that I have copied the data and you can take the data out of the descriptor and send it.

2. At this time, DMA will take out the data in the descriptor and send it out. After DMA has completed the operation on the descriptor, it will automatically set the OWN bit to 0, telling the CPU that DMA has finished sending the data and you can copy the next frame of data to the descriptor.

3. At this time, OWN is 0, repeat step 1

The entire sending process is coordinated in this way. In this way, there will be no data grabbing between DMA and CPU.

Bit 20 in DES 0 TCH : Second address chained

Used to indicate whether the second address in the descriptor is used to store the next descriptor address or the address of the second buffer.

When this bit is set to 1, it means that the second address in the descriptor is the next descriptor address, not the second buffer address. This is the chain structure used by ST.

The general RxDMA descriptor is as follows

Bit 14 of RDES1 in the regular RxDMA descriptor is used to indicate whether the second address in the descriptor is used to store a descriptor address or the address of the second buffer.

The descriptor is shown in the code in the stm32f2x7_eth.h file.

 /** --------------------------------------------------------------------------------**/  
 /**
  * @brief DMA descriptors types
 */
 /** --------------------------------------------------------------------------------**/   
 
 /**
  * @brief ETH DMA Descriptors data structure definition
 */
 typedef struct {
  __IO uint32_t Status; /*!< Status */
  uint32_t ControlBufferSize; /*!< Control and Buffer1, Buffer2 lengths */
  uint32_t Buffer1Addr; /*!< Buffer1 address pointer */
  uint32_t Buffer2NextDescAddr; /*!< Buffer2 or   next descriptor address pointer */
 /* Enhanced ETHERNET DMA PTP Descriptors */
 #ifdef USE_ENHANCED_DMA_DESCRIPTORS
  uint32_t ExtendedStatus; /* Extended status for PTP receive descriptor */
  uint32_t Reserved1; /* Reserved */
  uint32_t TimeStampLow; /* Time Stamp Low value for transmit and receive */
  uint32_t TimeStampHigh; /* Time Stamp High value for transmit and receive */
 #endif /* USE_ENHANCED_DMA_DESCRIPTORS */
 } ETH_DMADESCTypeDef;

03ST library descriptors

ST official Ethernet library stm32f2x7 uses the DMA descriptor of the link structure. Then in the Ethernet descriptor structure ETH_DMADESCTypeDef, Buffer1Addr is the address of the buffer, and Buffer2NextDescAddr is the address of the next descriptor.

As shown below.

Two DMA descriptor arrays are defined in stm32f2x7_eth.c, one for DMA reception and one for DMA transmission, as follows:

The sizes of receive and transmit descriptors are defined by the macros ETH_RXBUFNB and ETH_TXBUFNB, both of which are 5 by default.

We know that the Buffer1Addr member of the link structure Ethernet descriptor is used to store the buffer address, so where is the data buffer? This data buffer is also defined as an array, as follows:

The code that links them together links the descriptor and the buffer, that is, the following function constructs the descriptor label into a chain structure.

In the low_level_init function of ethernetif.c

The analysis is as follows

Global descriptor pointer, used to record the currently used descriptor

Descriptor describing the data packet (English: a structure used to store the last received packet descriptor information.)

Structure

The first one indicates the first descriptor of the data packet, the second one indicates the last descriptor of the data packet, and the third one indicates the number of data packet descriptors.

The final effect is as follows:

04FIFO

From the STM32 network controller block diagram, we can see two 2KB FIFOs, one transmit FIFO and one receive FIFO.

Transmit FIFO

Provides two FIFO data modes for frame transmission

1. Threshold mode: When the threshold is reached, data is transmitted as quickly as possible.
2. Store-and-Forward mode: A complete frame structure is stored in the FIFO.

The transmit FIFO of STM32 adopts Store-and-Forward mode.

Receive FIFO

The receive FIFO uses the Store-and-Forward mode.