5G infrastructure and the need for end-to-end programmability

By Alok Sanghavi, Senior Product Marketing Manager, Achronix Semiconductor

1. Introduction

We are currently in a transitional period for cellular connectivity, with a future of ubiquitous wireless connectivity emerging. Globally, the success of 2G, 3G and 4G has driven mobile phone usage to an incredible 7.5 billion units. Shockingly, this makes the number of mobile devices greater than the global population. Perhaps even more impactful is the impact that cellular connectivity is having on those who have previously been digitally disenfranchised; for example, in 2016 there was typically 1 landline telephone per 100 people in Sub-Saharan Africa, but 74 mobile connected devices.

Looking ahead to the next decade, wireless infrastructure will become even more ubiquitous and even fully integrated into every aspect of our daily lives with the advent of 5G, which continues the model of previous cellular standards (in terms of driving bandwidth) but also extends it to more devices and usage models.

Key trends include:

(1) Increased bandwidth demand for enhanced mobile broadband (eMBB) and other applications, especially instantaneous available bandwidth driven by 10 times the current throughput or higher.

• This will be the first wave of drivers brought about by 5G standardization, with 3GPP completing non-standalone (i.e. LTE-assisted) New Radio (NR) in 2017 and 5G standalone available in 2018, as shown in Figure 1.
• The deployment of 5G will also be phased in based on frequency band availability, with sub-6 GHz being deployed first, followed by contiguous bands of millimeter wave (mmWave) frequencies to support key eMBB applications at a later stage.

Figure 1: ITU and 3GPP timelines for 5G

(2) Connectivity to a large number of devices with the advent of cellular connectivity for the Internet of Things (IoT). It is estimated that there will be 50 billion cellular-connected devices by 2020. Some of these needs can be met by existing standards, but also by the existing specification of massive machine-type communications (mMTC) in Release 16.

(3) New application models are also emerging, which place new demands on mobile devices and their cellular wireless infrastructure. Examples include:

• Low-bandwidth, low-power requirements for connecting multiple battery-powered IoT endpoints to enable mMTC-related connectivity and monitoring;
• High-reliability, low-latency cellular networks for vehicle-to-vehicle and vehicle-to-infrastructure connectivity (C-V2X) to complement existing V2X solutions;
• High reliability, low latency support for emerging applications such as remote surgery and augmented/virtual reality.

The latter two types of applications will be addressed by the upcoming 3GPP Ultra-Reliable, Low-Latency Connectivity (URLLC) standard.

(4) New demands for edge analytics and mobile edge computing (MEC). The computing focus is shifting from the previous paradigm of sending data to centralized computing resources for processing to a new paradigm of moving to distributed computing resources located near the origin of data generation. The reasons for this shift are multifaceted: the stringent latency requirements of emerging applications, the increasing amount of data, and the desire to optimize scarce network resources, among many others.

2. Baseband

In this paper, we consider how to successfully address the unique demands of 5G through an SoC architecture with a high-performance CPU subsystem and hardware processing units including FPGA reprogrammable acceleration.

The baseband takes data from the network interface (e.g. Ethernet) and converts it into complex samples that are transmitted to the RF front end for inbound/outbound transmission via the fronthaul interface. The following high-level schematic includes the transmitter for the LTE downlink (Figure 2a), and the receiver for the uplink (Figure 2b).

(a) Downlink

(b) Uplink

Figure 2: High-level schematic of baseband processing

3. Case Study of Baseband L1 Processing

Here, we illustrate how to map baseband processing (especially Layer-1) onto key processing components such as processor subsystems, CPU and DSP cores, as well as fixed and flexible hardware acceleration, as shown in Figure 3.

Figure 3: Key baseband processing components

1. Fronthaul (antenna interface) connection

In addition to the processing components described previously, there is also a flexible antenna interface functional block: this is what is needed to connect the baseband and the radio unit. Traditionally, this is the Common Public Radio Interface (CPRI), sometimes the Open Base Station Architecture Initiative (OBSAI) compliant part.

However, more and more schemes are turning to specify a more flexible fronthaul interface to allow different mappings between the baseband and RF front end (as shown in Figure 4). IEEE has continued to follow up on the next-generation fronthaul interface NGFI (IEEE1914), including the IEEE1914.1 standard for packet-based fronthaul transmission networks and the IEEE1914.1 standard for Ethernet radio (RoE) encapsulation and mapping. At the same time, there are other industry projects that specify 5G fronthaul interfaces and can be shared, such as eCPRI.

Given the various specifications, standards, and requirements facing the fronthaul interface, FPGAs are well suited for its application and are often used to support this interface, as shown in Figure 3.

2. Discrete architecture accelerates 5G time to market

Figure 4 maps the processing elements required for 5G into a discrete architecture with separate devices, including a CPU SoC, auxiliary FPGA acceleration, and antenna interface. This configuration reflects an implementation that can be deployed in 5G prototyping and early production before optimized 5G application-specific integrated circuits (ASICs) become available.

(1) The CPU system-level chip includes: an Arm processor combination and DSP cores for Layer-1 processing and hardened accelerators for fixed, well-defined functions.

In this example, it is assumed that an existing 4G ASIC SoC is available and therefore has generic acceleration (e.g. MACSEC) as well as LTE specific acceleration: forward error correction (especially turbo codec), fast Fourier transform and discrete Fourier transform to support SC-FDMA on the uplink.

(2) Flexible antenna interface

As mentioned earlier, the fronthaul antenna interface is well suited for implementation with an FPGA. This is configured online, with data coming out of the RF unit (on the uplink) and then converted to a protocol such as Ethernet with a standard connection.

(3) Hardware Acceleration FPGA

• The auxiliary acceleration FPGA implements all necessary compute-intensive functions that are not available on the baseband SoC. This can be 5G-specific functions or functions that were not previously planned.
• In the example shown here, the CCIX interconnect is used. This standard allows processors based on different instruction set architectures to extend the benefits of cache coherent, peer processing to a variety of acceleration devices including FPGAs and custom ASICs.

Figure 4: Discrete architecture that accelerates 5G time to market

3. 5G Implementation Based on Chiplet

Figure 5 shows a similar architecture to that shown in Figure 4, but reconfigured using a chiplet-based approach. In this case, a higher bandwidth, lower latency, and lower power interface connects the CPU SoC die to the auxiliary hardware acceleration chiplet. The FPGA device that supports the fronthaul connection to the RF unit can be integrated into the package in this example, but in reality, it can be the same chiplet device as the hardware acceleration chiplet if there are enough resources.

Figure 5: Chiplet-based approaches enable higher levels of integration

The two main technologies used for package integration are using either a silicon interposer or an organic substrate, and some form of ultra-short reach (USR) transceiver.

4. Fully integrated 5G implementation

The baseband architecture is shown in Figure 6. This approach includes the same processing elements as before, with the same functionality, but with an embedded FPGA (eFPGA) integrated within the chip.

Figure 6: Heterogeneous multi-core SoC for 5G baseband using monolithic integration

This tightly integrated monolithic approach has many advantages. The interface has higher bandwidth, lower latency, and lower energy per bit compared to a chiplet-based approach. In addition, the resource mix can be tailored to the specific application under consideration, so unnecessary interfaces, memories, and core logic cells are avoided. This allows for the lowest unit cost of the three architectures considered above.

As mentioned earlier, the main goals now are to provide faster time to market, greater flexibility, and future availability. Time to market is accelerated because the SoC can be taped out earlier and because late modifications (such as the emergence of Polar codes in the 5G standard) can be made to the eFPGA instead of a finished and fixed ASIC. Flexibility from new or unanticipated algorithms (such as new encryption standards) can be addressed by embedded programmable logic instead of software or external FPGAs. Future availability can extend the life cycle of the SoC because high-volume emerging requirements such as new standards such as URLLC and mMTC can be addressed by existing products without the need for new development.

Summarize

The tight coupling of CPU and programmable acceleration (embedded or stand-alone FPGA) enables developers to create a platform product that can be applied to multiple different markets. This increases the market applicability of specific products and improves the return on development investment. This can even position (or reposition) the market after tape-out, that is, the inherent flexibility provided by programmability can support considerable innovation space.

Perhaps more importantly from a 5G perspective, highly programmable solutions can speed up time to market. For example, there is no need to postpone SoC tape-outs until standards are finalized, and subsequent changes can be implemented in software or programmable hardware. This is a significant advantage for the increasing pressure faced by early 5G deployments and the emergence of new standards.