Let's talk about the communication protocol I2C subsystem

I2C Transfer

Definition of timing

To explore the I2C protocol in depth, you must have a deep understanding of the definitions of various times (F/S-mode)

Sr restarts, S starts, and P stops.

Note: When SCL is high, SDA is high, which is 1, and low, which is 0. During SCL low, SDA changes data.

Note: The start condition is easy to understand. Repeating the start condition means there is no STOP, then a START, and then sending another slave device ID to access other slave devices.

Defining Terms

1. Data Validity

During the SCL high level period, SDA must be stable, so in general, the SCL high level width is small and the SDA high level width is large, which is also the case when viewed with an oscilloscope.

2. Start condition and stop condition

Start condition: When SCL is high, SDA changes from high to low.

Stop condition: When SCL is high, SDA changes from low to high.

Generally, each time a byte (8 bits) is transmitted, it will restart. SDA changes data during the low level period of SCL, and cannot change data during the high level period of SCL, otherwise it will be considered as a start and stop condition.

• The transfer length must be one byte (8 bits)
• Unlimited bytes per transfer
• Data must be transmitted starting with the MSB, that is, the highest bit is transmitted first.
• The slave can hold the clock line SCL low, forcing the master to enter a wait state.

3.ACK or NACK

After each byte is transmitted, the slave device must respond with ACK or NACK.

ACK: After transmitting 8 bits, at the ninth bit, SCL is high. If SDA is low, it means ACK is responded.

NACK: After transmitting 8 bits, at the ninth bit, SCL is high. If SDA is high, it means a NACK response.

4.write data

5. read data

6. Composite Format

7.I2C Transfer Regulation

• Start with START condition
• End with STOP condition
• The first byte transmitted is 7-bit slave address + 1-bit read/write bit
• Each device on the bus will compare the 7-bit address after the STRAT signal with its own address to see if it matches.
• Each byte (8 bits) will be followed by ACK or NACK
• After a START signal or repeated START signal, the slave must reset its bus logic
• A START followed by a STOP signal is an illegal format.
• The host master can generate a repeated START signal + another device address instead of a STOP signal to directly start accessing another device.

8.10-bit addressing

The analysis is as follows:

A9-A0 indicates 10 bits address

9. Oscilloscope waveform

10. Supplement

I2C does not support the slave device to initiate an interrupt on the SCL and SDA buses to notify the master device to read data. Slave devices with interrupt requirements need to connect an additional interrupt line to notify the master that the data is ready and let the master initiate the data read operation.