I2C TransferDefinition of timingTo explore the I2C protocol in depth, you must have a deep understanding of the definitions of various times (F/S-mode)
Sr restarts, S starts, and P stops. Note: When SCL is high, SDA is high, which is 1, and low, which is 0. During SCL low, SDA changes data. Note: The start condition is easy to understand. Repeating the start condition means there is no STOP, then a START, and then sending another slave device ID to access other slave devices. Defining Terms1. Data ValidityDuring the SCL high level period, SDA must be stable, so in general, the SCL high level width is small and the SDA high level width is large, which is also the case when viewed with an oscilloscope. 2. Start condition and stop conditionStart condition: When SCL is high, SDA changes from high to low. Stop condition: When SCL is high, SDA changes from low to high. Generally, each time a byte (8 bits) is transmitted, it will restart. SDA changes data during the low level period of SCL, and cannot change data during the high level period of SCL, otherwise it will be considered as a start and stop condition.
3.ACK or NACKAfter each byte is transmitted, the slave device must respond with ACK or NACK. ACK: After transmitting 8 bits, at the ninth bit, SCL is high. If SDA is low, it means ACK is responded. NACK: After transmitting 8 bits, at the ninth bit, SCL is high. If SDA is high, it means a NACK response. 4.write data5. read data6. Composite Format7.I2C Transfer Regulation
8.10-bit addressingThe analysis is as follows: A9-A0 indicates 10 bits address 9. Oscilloscope waveform10. SupplementI2C does not support the slave device to initiate an interrupt on the SCL and SDA buses to notify the master device to read data. Slave devices with interrupt requirements need to connect an additional interrupt line to notify the master that the data is ready and let the master initiate the data read operation. |
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