STM32 Network SMI Interface

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01 Introduction to Ethernet

The Ethernet peripherals of STM32F20X and STM32F21 can receive and send data according to the IEE802.3-2002 standard.

Ethernet provides a complete and flexible peripheral to meet different applications and requirements. It supports two standard industrial interfaces to the outside world (PHY): the media independent interface (MII) and the refined media independent interface (RMII) defined in the IEEE802.3 specification are used by default. It can be used for a large number of needs, such as switches, network interface cards, etc.

Ethernet meets the following standards:

• IEEE 802.3-2002, for Ethernet MAC.
• IEEE 1588-2008 standard for specifying the accuracy of networked clock synchronization.
• AMBA 2.0 for AHB master/slave ports.
• RMII Alliance's RMII specification.

02STM32F207 ETH Introduction

The STM32F207 supports the MII interface and the RMII interface. The STM32F207 Ethernet peripheral includes a MAC802.3 (Media Access Control) and a DMA controller. It supports the MII and RMII interfaces by default, and switches through a selection bit (refer to the SYSCFG_PMC register).

The DMA controller is connected to the memory through the AHB master-slave interface and the core. The AHB master interface controls the data transfer, and the AHB slave interface is used to access the control and status register (CSR) space.

Before the MAC core sends data, the data is sent to the FIFO buffer via DMA. Similarly, the receive FIFO stores Ethernet data frames received over the line until these data frames are transferred to the system memory via DMA.

The Ethernet peripheral also includes an SMI for communicating with an external PHY. Through a set of register configurations, the user can select different modes and functions of the MAC and DMA controllers.

When using Ethernet, the AHB clock must be at least 25MHZ.

Below is the block diagram of ETH

About AHB connection information:

Area 1: We call it the SMI interface, which is used to configure the external PHY chip.

Area 2: is the data exchange interface, which is the MII interface and RMII interface we mentioned above.

03SMI interface

3.1. Station Management Interface: SMI

The station management interface allows any PHY register request via the 2-wire clock and data lines. This interface supports up to 32 PHYs.

The application can select a PHY from among the 32 PHYs and then select a register from among the 32 registers contained in any PHY to send control data or receive status information. Only one register in a PHY can be addressed at any given time.

The MDC clock line and the MDIO data line are both used as alternate function I/O in the microcontroller:

MDC: A periodic clock that provides reference timing for data transmission at a maximum frequency of 2.5 MHz. The minimum high time and the minimum low time of MDC must both be 160 ns. The minimum period of MDC must be 400 ns. In the idle state, the SMI management interface drives the MDC clock signal low.

MDIO: Data input/output bit stream used to transfer status information to/from the PHY device synchronously via the MDC clock signal.

3.2 SMI frame structure

The following figure shows the frame structure of read and write operations. Bit transmission must be from left to right.

Preamble (32-bit preamble): Each transmission (read or write) must start with a preamble, which is 32 consecutive logic '1' signals on the MDIO line and 32 clock signals on the corresponding MDC line. This part of the signal is used to establish synchronization with the PHY device.

Start: The start character of a frame is defined as '01', which means that the MDIO line drops from logic '1' to '0' and then returns to '1' to mark the transmission.

start.

Operation: It is used to define the type of operation: read or write.

PADDR: The PHY address has 5 bits, which can distinguish 32 PHYs. The high bit is sent and received first.

RADDR: The register address has 5 bits and can address 32 independent registers. The high bit is sent and received first.

TA: A 2-bit turn character inserted between RADDR and data (DATA) to avoid conflicts during read operations. During read operations, during the 2-bit time of TA, the MAC controller maintains the high-impedance state of the MDIO line, and the PHY device maintains the high-impedance state of 1 bit first, and outputs a '0' signal at the second bit. During write operations, during the 2-bit time of TA, the MAC controller drives the MDIO line to output a '10' signal, and the PHY device maintains a high-impedance state.

DATA: 16-bit data field. The first bit sent and received is the 15th bit of the ETH_MIID register.

Idle position: The MDIO line remains in high impedance state. All tri-state drivers are canceled, and the MDIO line is guaranteed to be in logic '1' by the pull-up resistor of the PHY.

3.3 SMI write operation

When the application sets the MII write and busy bits (Ethernet MAC MII address register (ETH_MACMIIAR)), the SMI interface transmits the PHY address and PHY register address to the PHY, and then transmits the data (Ethernet MAC MII data register (ETH_MACMIIDR)). During the data transmission process of the SMI interface, the contents of the MII address register and the MII data register cannot be modified; during this process (the busy bit is high), the write operation to the MII address register or the MII data register will be ignored and will not affect the correct completion of the entire transmission. When the write operation is completed, the SMI interface will clear the busy bit to inform the application.

The following figure describes the frame format during write operation.

3.4 SMI Read Operation

When the program sets the MII busy bit of the Ethernet MACMII address register (ETH_MACMIIAR) to '1' and keeps the MII write bit to '0', the SMI interface sends the PHY address and PHY register address to perform the operation of reading the PHY register. During the entire transmission process, the application cannot modify the contents of the MII address register and the MII data register. During the transmission process (the busy bit is high), the write operation to the MII address register or the MII data register will be ignored and will not affect the correct completion of the entire transmission. After the read operation is completed, the SMI interface will clear the busy bit and update the data read back from the PHY to the MII data register.

The following figure describes the frame format of the read operation

3.5 SMI clock selection

MAC starts management write/read operations. The SMI clock is a divided clock whose clock source is the application clock (AHB clock). The division factor depends on the clock range set in the MII address register. Since we are talking about the clock here, let's mention it again: when using Ethernet, the AHB clock must be at least 25MHZ.

04Code

The initialization of the MII interface of the STM32 network port is very simple.

Initialize GPIO.

 RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOA | RCC_AHB1Periph_GPIOC |RCC_AHB1Periph_GPIOF, ENABLE); 
 
 /* Enable SYSCFG clock */
 RCC_APB2PeriphClockCmd(RCC_APB2Periph_SYSCFG, ENABLE);
 GPIO_InitStructure.GPIO_Pin = GPIO_Pin_2;
 GPIO_Init(GPIOA, &GPIO_InitStructure);
 GPIO_PinAFConfig(GPIOA, GPIO_PinSource2, GPIO_AF_ETH); 
 
 GPIO_InitStructure.GPIO_Pin = GPIO_Pin_1;
 GPIO_Init(GPIOC, &GPIO_InitStructure);
 GPIO_PinAFConfig(GPIOC, GPIO_PinSource1, GPIO_AF_ETH);

Because the MII interface requires MAC cooperation, the clock that enables the MAC is required.

 RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_ETH_MAC |RCC_AHB1Periph_ETH_MAC_Tx |RCC_AHB1Periph_ETH_MAC_Rx, ENABLE);

Read and write functions of the MII interface.

 ETH_ReadPHYRegister(uint16_t PHYAddress, uint16_t PHYReg)
 uint32_t ETH_WritePHYRegister(uint16_t PHYAddress, uint16_t PHYReg,uint16_t PHYValue)

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