Let’s talk about PHY register, do you know it?

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In the previous article, we explained the network peripherals of STM32.

STM32 cannot communicate with the network when it only has network peripherals, because STM32 only provides SMI interface, MII and RMII interface. We also need an external network chip to communicate with it, referred to as PHY chip. The PHY models I am familiar with are: RTL8201F, RTL8201E, RTL8201G, DP83848, YT8512C, etc. I originally planned to explain RTL8201F, but there is too much content, so I will talk about the PHY register first.

Why doesn't STM32 integrate PHY?

PHY (Port Physical Layer), which can be called port physical layer in Chinese.

1. The PHY chip is an analog chip that needs to convert the differential signal of the network cable into a digital signal. If it is integrated, the chip area will increase. If the power consumption is to be reduced, a higher chip manufacturing process is required, which will directly increase the chip cost.

2. Not all STM32 users need to use the network, and integrating PHY will increase costs.

Therefore, the fact that STM32 does not integrate PHY is not a technical problem, but the result of various considerations.

Aren't there any MCUs with integrated PHY?

Yes, TI's LM3S8962.

Let's talk about PHY registers. External PHY chip registers are divided into 3 types:

Basic: Basic registers

Extended: Extended register

Vendor-spcififc: Vendor-specific registers

The following description is included in the 2012 version of the 802.3 protocol.

Different manuals have different descriptions of the basic registers. According to the description in the figure above of 802.3-2012, the basic registers are the controller register (register 0) and the status register (register 1). In the GMII (Gigabit Ethernet) interface, the CNOOC extended status register (register 15).

This article mainly explains the basic registers of PHY based on the 802.3-2012 protocol, not based on a specific chip.

The positions of register 0 and register 1 in the protocol document are as follows:

The 802.3-2012 protocol mentioned above can be downloaded from the IEEE official website

https://standards.ieee.org/

Or download via Baidu Cloud

Link: https://pan.baidu.com/s/1Nr_KHse32zysBKZ0btPceg

Extraction code: xhin

01 Control register (register 0)

Register 0 is the PHY control register. The main working status of PHY can be set through ControlRegister.

bit15 Rset

When bit15 is 1, it means that the PHY is reset. Bit15 controls the PHY reset function. Writing 1 to this position implements the PHY reset operation. After the reset, the other control and status registers of the port PHY will be restored to the default values. Each PHY reset should be completed within 0.5s. During the reset process, Bit15 remains 1. After the reset is completed, this bit should be automatically cleared. Generally, when changing the working mode of the port (such as rate, duplex, flow control or negotiation information, etc.), after setting the register at the corresponding position, it is necessary to reset the PHY through the Reset bit to make the configuration effective.

The PHY is not required to accept write transactions to the control register until the reset process is complete, and writes to bits other than bit 15 in the control register may have no effect until the reset process is complete.

bit14 Loopback

Loopback is a commonly used function in debugging and fault diagnosis. After Bit14 is set to 1, the connection between PHY and external MDI will be logically disconnected, and the data sent from MAC through MII/GMII (or other MAC/PHY interfaces) will not be sent to MDI, but will be looped back inside PHY (usually in PCS) to the MII/GMII receiving channel of this port.

The Loopback function can be used to check whether the MII/GMII and PHY interface parts are working properly, and can be used to locate faults when the port is blocked. It should be noted that in many cases, after the PHY is set to Loopback, the port may be Linkdown, and the MAC cannot send frames to the port. In this case, you need to set the port to ForceLink up to use the Loopback function.

bit13 Speed ​​Selection(LSB)

Bit13 and Bit6 are used together to implement the rate control function of the port. The specific corresponding relationship is shown in the figure below.

It should be noted that SpeedSelection only works when auto-negotiation is turned off. If auto-negotiation is set to Enable, this setting will not work.

In addition, the modification of SpeedSelection often requires resetting the port for the configuration to take effect. Therefore, when setting this position, you need to check the auto-negotiation settings and reset the port through Bit15.

bit12 Auto-Negotiation Enable

Auto-negotiation (AN) switch. Setting it to 1 means turning on the AN function, and the port's working mode is determined by auto-negotiation with the connected peer. If it is set to 0, the auto-negotiation function is turned off, and the port's working mode is determined by the configuration of the corresponding position in ControlRegister. It must be noted that for 1000BASE-T interfaces, auto-negotiation must be turned on.

bit11 Power Down

Port work switch: Setting it to 1 will put the port into PowerDown (low power consumption state) mode. Under normal circumstances, the MII and MDI of PHY will not send data to the outside in PowerDown mode. PowerDown mode is generally used when the software shuts down the port. It should be noted that when the port recovers from PowerDown mode, it is necessary to reset the port to ensure reliable connection of the port.

bit10 Isolate

Isolation status switch: Changing the position to 1 will cause the PHY and MII interfaces to be electrically isolated. Except for the signals of the MDC/MDIO interface, other MII pins are in high impedance state. IEEE802.3 does not regulate the state of the MDI interface during Isolate, and the MDI end may still be operating normally at this time. Isolate is not used in actual applications. In addition, it is worth noting that since the mainstream MAC interface of many 100M PHY chips is SMII/S3MII, the interfaces of the 8 ports are interrelated. Setting Isolate on one port may affect the normal use of other ports. Therefore, be careful not to change the state of bit10 at will during use.

bit9 Restart Auto-Negotiation

Restart auto-negotiation switch: Setting Bit9 to 1 will restart the auto-negotiation process of the port, of course, the premise is that Auto-NegotiationEnable is enabled. Generally, after modifying the auto-negotiation capability information of the port, setting Bit9 to 1 to restart the auto-negotiation will enable the port to establish a link according to the new configuration.

bit8 Duplex Mode

Duplex mode setting: Bit8 is set to 1 to set the port to full duplex, and to 0 to set the port to half duplex. Like the SpeedSelection setting, the DuplexMode setting only works when auto-negotiation is turned off. If auto-negotiation is set to Enable, the setting does not work, and the port's duplex mode is determined by the AN result. Modifications to DuplexMode also require resetting the port to take effect.

bit7 Collision Test

Collision signal (COL) test switch: When the COL signal needs to be tested, Bit7 can be set to 1, and the PHY will output a COL pulse for testing. In actual test operations, the port can also be configured to half-duplex state to test the COL signal by sending frame collisions, so this configuration has little practical value.

bit6 Speed ​​Selection(MSB)

Together with Bit13, it realizes the rate control function of the port.

bit5 Unidirectional enable

When bit 12 is 1 or bit 8 is 0, this bit is ignored.

When bit 12 is 0 and bit 8 is 1:

1: Enables transmission from the MII interface regardless of whether the PHY determines that a valid link has been established

0: Enable transmission from the MII interface only when the PHY determines that a valid link has been established

Bits 4:0 reserved

Reserved bits, they shall be written as zero and shall be ignored when read; however, the PHY shall return the value zero in these bits.

02 Status register (register 1)

Register 1 is the PHY status register, which mainly contains the status information of PHY.

bit15 100BASE-T4

The ability of the PHY to perform link transmission and reception using the 100BASE-T4 signaling specification. 1: Capable; 0: Not capable.

bit14 100BASE-X Full Duplex

The ability of the PHY to perform full-duplex link transmission and reception using the 100BASE-X signaling specification. 1: Capable; 0: Not capable.

bit13 100BASE-X Half Duplex

The ability of the PHY to perform half-duplex link transmission and reception using the 100BASE-X signaling specification. 1: Capable; 0: Not capable.

bit12 10Mb/s Full Duplex

The PHY is capable of performing full-duplex link transmission and reception while operating at 10Mb/s. 1: Capable; 0: Not capable.

bit11 10Mb/s Half Duplex

The PHY is capable of performing half-duplex link transmission and reception while operating at 10Mb/s. 1: Capable; 0: Not capable.

bit10 100BASE-T2 Full Duplex

The PHY has the ability to perform full-duplex link transmission and reception using the 100BASE-T2 signaling specification. 1: Capable; 0: Not capable.

bit9 100BASE-T2 Half Duplex

The PHY has the capability to perform half-duplex link transmission and reception using the 100BASE-T2 signaling specification. 1: Capable; 0: Not capable.

bit8 External Status

• 1: Enable register 15
• 0: Disable register 15

bit7 Unidirectional ability

1: The PHY is capable of encoding and transmitting data from the PHY over the MII interface regardless of whether the PHY has determined that a valid link has been established.

0: Enable transmission from the MII interface only when the PHY determines that a valid link has been established

bit6 MF Preamble Suppression

1: The PHY is able to accept Management Frames regardless of whether they are preceded by a preamble pattern.

0: The PHY MUST NOT accept management frames unless they are preceded by the preamble pattern.

Preamble mode.

This is described in 22.2.4.5.2 of the official document. You can check it yourself.

In fact, we have explained this preamble before, as shown in the article "STM32 Network SMI Interface" as shown below. It is recommended that students who have not read this article read it.

bit5 Auto-Negotiation Complete

AN completion status indicator bit: Bit5 indicates whether the port AN process is completed. In the case of ANEnable, Bit5=1 indicates that the auto-negotiation process has been successfully completed, and at this time, other registers related to the PHY and Link status are correct and reliable. If the AN process is not completed, these status information may be wrong. During debugging and abnormal fault handling, the status of this bit register can be used to determine whether the AN is successful, so as to further check whether the AN-related settings are correct, or whether the AN function of the chip is normal.

bit4 Remote Fault

Remote error indication bit: Bit4 = 1 indicates an error at the other end (LinkPartner). The specific type of error and error detection mechanism are not defined in the specification and are left to the PHY manufacturer to define. Generally, manufacturers will indicate more detailed error types in other registers (Register 16-31 is defined by the manufacturer). In port-related fault verification, RemoteFault is an important indication information. The RemoteFault information of the interconnected parties (possibly with other specific error indications) can help locate the cause of the fault.

bit3 Auto-Negotiation Ability

1: PHY enables auto-negotiation

0: PHY does not enable auto-negotiation

bit2 Link Status

Link status indicator bit: Bit2 = 1 represents the port Linkup, 0 represents the port Linkdown. In practical applications, Bit2 is generally used to determine the port status. Moreover, general MAC chips also determine the port Link status by polling the PHY register value (this process may have different names, such as BCM called LinkScan, and Marvell called PHYPolling.) As mentioned earlier, in the case of ANEnable, the LinkStatus information is only correct and reliable when the Auto-NegotiationComplete indication has been completed, otherwise there may be an error.

bit1 Jabber Detect

1: The shaking (stabbing) state is detected

0: No jitter (jab) status detected

bit0 Extended Capability

1: The PHY provides an extended feature set, accessible through an extended register set.

0: No extension registers are provided.

03 Register 15

Register 15 Main Mode Gigabit Ethernet mode, the status of the PHY.

As shown in the figure above, register 15 mainly describes the status of PHY in Gigabit Ethernet mode, and its specific meaning is similar to the relevant bits of register 1.

bit15 1000BASE-X Full Duplex

The ability of the PHY to perform full-duplex link transmission and reception using the 1000BASE-X signaling specification. 1: Capable; 0: Not capable.

bit14 1000BASE-X Half Duplex

The ability of the PHY to perform half-duplex link transmission and reception using the 100B0ASE-X signaling specification. 1: Capable; 0: Not capable.

bit13 1000BASE-T Full Duplex

The PHY is capable of performing full-duplex link transmission and reception using the 1000BASE-T signaling specification. 1: Capable; 0: Not capable.

bit12 1000BASE-T Half Duplex

The PHY has the ability to perform half-duplex link transmission and reception using the 1000BASE-T signaling specification. 1: Capable; 0: Not capable.

Bits 11:0 reserved

Reserved bit, ignored when reading.

04Other registers

In addition to the basic registers, the 802.3-2012 protocol also mentions other registers, which are briefly described here without elaborating on them.

Register 2, 3: Chip ID register

Registers 2 and 3 are PHYID registers. From the kernel code, we know that register 2 (PHYID1) is the upper 16 bits, while register 3 (PHYID2) is the lower 16 bits. As the identification of the PHY chip, they are generally considered to be of little use. In the past, the same main CPU was used with different PHY combinations and different boards, using the same kernel. Here, PHYID can be used to distinguish them.

Register 4: Auto-Negotiation Advertisement Register

This register stores the characteristics and capabilities of the PHY itself, such as PHY supports flow control, 100M full-duplex/half-duplex, 10M full-duplex/half-duplex, etc.

When set to auto-negotiation enabled, it is advertised on MDI via FLP. If not enabled, the configuration of this register has no effect.

Register 5: Auto-negotiation peer capability notification register

This register is similar to register 4. It indicates the features and capabilities of the peer (switch or PC). It should also be noted that the information in this register is only valid when auto-negotiation is enabled. Since this register indicates the status of the peer, the value of the register is generally designed to be read-only, but some chips, such as the flow control bit 5.10 FCS of the DM9000, are readable and writable.

This register is mainly used to understand the situation of the other end. When a problem occurs, you can understand the other party's information and roughly locate the scope, instead of blindly looking for the cause yourself. If the switch on the other end is really faulty, this register is a strong on-site evidence.

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